1. Field of the Invention
The present invention relates to a photoelectric converting apparatus and, more particularly, to a photoelectric converting apparatus having a plurality of photoelectric conversion elements which can accumulate the photoelectrically converted charges. The invention is suitably used in a photoelectric converting apparatus for use in, for instance, a focal point detecting apparatus of a camera, an image reading apparatus, or the like.
2. Related Background Art
Hitherto, such a kind of apparatus has already been proposed in, for instance, Japanese Patent Application No. 63-47644 by the applicant of the present invention.
FIG. 7 shows an equivalent circuit diagram of a photoelectric conversion element array shown in Japanese Patent Application No. 63-47644.
In FIG. 7, reference numerals 1--1 to 1-n denote a photo transistor array (cells) of the accumulation type having a structure such that a common power source is connected to collectors and the photoelectrically converted charges are accumulated into control electrode regions (bases) and can be read out from main electrode regions (emitters). A practical content of the above structure has been described in detail in, for instance, Japanese Laid-open Patent Gazette Nos. 62-128678 and 62-113468, Japanese Patent Application Nos 61-168286, 61-219668, and 61-219669, and the like. Reference numerals 2-1 to 2-n denote PMOS switches for connecting the base of each of the bipolar transistors constructing the photo transistor array 1 to a power source V.sub.c and resetting when a signal .phi..sub.res is given. Reference numerals 3-1 to 3-n denote NMOS switches, connected to the emitters of the above bipolar transistors, for taking out the accumulated signals to the post stage synchronously with a signal .phi..sub.t. Reference numerals 4-1 to 4-n denote NMOS switches, connected serially to the NMOS switches 3-1 to 3-n, for sending an image signal to a read-out line 7. Reference numerals 5-1 to 5-n denote accumulation capacitors, connected between the nodes of the NMOS switches 3-1 to 3-n and the NMOS switches 4-1 to 4-n and the ground, for reading out the signal every pixel. Reference numeral 6 denotes a shift register for sequentially turning on the NMOS switches 4-1 to 4-n and successively reading out the image signal; 8 an NMOS switch for initializing by connecting the read-out line 7 to which output terminals of the NMOS switches 4-1 to 4-n are commonly connected to the ground when a signal .phi..sub.hrs is given; 9 an output amplifier for amplifying the image signal which was output to the read-out line 7; and 10-1 to 10-n NMOS switches for connecting the emitters of the photo transistor array 1--1 to 1-n to the ground when a signal .phi..sub.vrs is given. Reference numeral 107 indicates a max/min values detection circuit comprising: minimum value detection circuits 11-1 to 11-n, maximum value detection circuits 12-1 to 12-n, and output amplifiers 13 and 14.
FIG. 8 shows a construction of one unit of the minimum value detection circuit.
As shown in FIG. 8, one minimum value detection circuit comprises one differential amplifier 30 and one PNP type transistor 31. The differential amplifier 30 comprises a constant current circuit 411, PMOS transistors 407 and 408, and NMOS transistors 409 and 410. An emitter line of the PNP type transistor 31 is fed back to an inversion input (I.sub.n2) of the differential amplifier 30. The emitters of the pixel trains of the photo transistor array 1--1 to 1-n are input to a non-inversion input (I.sub.n1) When the level of the non-inversion input (I.sub.n1) of the differential amplifier 30 is higher than the level of the inversion input (I.sub.n2), a base potential of the PNP type transistor 31 is shifted to about the power source voltage level, thereby turning off the PNP type transistor 31. Therefore, no voltage is developed in an input of the output amplifier 13 shown in FIG. 7. An output voltage is caused in the PNP type transistor 31 in the case where the lowest voltage was given to the non-inversion input (I.sub.n1) of the differential amplifier 30. In this case, the minimum value is detected.
FIG. 9 shows a construction of one unit of the maximum value detection circuit.
As shown in FIG. 9, one maximum value detection circuit comprises one differential amplifier 32 and one NPN type transistor 33. The differential amplifier 32 comprises a constant current circuit 401, PMOS transistors 402 and 403, and NMOS transistors 404 and 405. An emitter line of the NPN type transistor 33 is fed back to the inversion input (I.sub.n2) of the differential amplifier 32 and is used as an output line. The emitters of the pixel train are connected to the non-inversion input (I.sub.n1). When the level of the non-inversion input (I.sub.n1) of the differential amplifier 32 is lower than the level of the inversion input (I.sub.n2), a base potential of the NPN type transistor 33 is reduced to about the voltage level of a negative power source, so that the NPN type transistor 33 is turned off. An output voltage is caused in the NPN type transistor 33 when the highest voltage was applied to the non-inversion input (I.sub.n1) of the differential amplifier 32. In this case, the maximum value is detected. R denotes a load resistor in each of the minimum value detection circuit and the maximum value detection circuit.
FIG. 10 is a timing chart for explaining the operation of the photoelectric conversion element array in FIG. 7.
First, a resetting operation is executed. By turning on the PMOS switches 2-1 to 2-n by setting the signal .phi..sub.res to the low level for a period of time from t.sub.1 to t.sub.2, base potentials of the photo transistor array (hereinafter, referred to as a pixel train) 1--1 to 1-n are fixed to the potential of V.sub.c.
Then, by setting the signals .phi..sub.vrs and .phi..sub.t to the high level (ON) for a period of time from t.sub.3 to t.sub.4, the NMOS switches 10-1 to 10-n and 3-1 to 3-n are made conductive, the accumulation capacitors 5-1 to 5-n are connected to the grounded, and the residual charges are reset. After completion of the resetting for the bases and emitters of the pixel train 1--1 to 1-4, the next accumulating operation is started.
In the accumulating operation, the photoelectrically converted charges are accumulated into the base regions of the pixel train 1--1 to 1-n. At this time, the bases and emitters of the pixel train are in the floating state (capacitive load state) and the voltage to which the base potential was reflected is caused in the emitters.
When the signals are sequentially read out, the NMOS switches 4-1 to 4-n are sequentially turned on by the shift register 6 and the signal charges accumulated in the accumulation capacitors 5-1 to 5-n are read out to the read-out line 7. Each time the signal .phi..sub.CK is input, the shift register 6 sequentially selects the NMOS switches 4-1 to 4-n. Just before the NMOS switches 4-1 to 4-n are selected, the NMOS switch 8 is turned on by the signal .phi..sub.hrs and the charges remaining in the read-out line 7 are reset.
In Japanese Patent Application No. 63-47644, there has been proposed a method whereby by constructing a photoelectric converting apparatus as shown in FIG. 11 or 12 by using the photoelectric conversion element array having the max/min values detection circuit as mentioned above, the accumulation time is controlled so as to keep differences between a bright portion, and a dark portion constant a pattern of an object, and only a characteristic portion of the pattern is A/D converted,
In the above apparatuses, a discrimination regarding whether the signal charges are accumulated until a proper level or not is performed by checking to see if a difference between the maximum and minimum levels of the accumulation levels of the photoelectric conversion element array has reached the reference level V.sub.ref or not. Reference numeral 102 denotes a differential amplifier to calculate the difference between a maximum value V.sub.max and a minimum value V.sub.min. Reference numeral 103 indicates a comparator for comparing an output level of the differential amplifier 102 and the predetermined reference level V.sub.ref, thereby discriminating whether the output level has reached the proper accumulation level or not. When a signal .phi..sub.comp of the comparator 103 is inverted, a microcomputer 104 detects that the signal charges were accumulated until the reference level. Then, the microcomputer 104 sends the pulse .phi..sub.t to finish the accumulation to a photoelectric conversion element array 101. At the same time, the microcomputer 104 sends a signal SH to a memory circuit 105, thereby storing the V.sub.min level at the time of completion of the accumulation. Then, the signals .phi..sub.CK and .phi..sub.hrs are sent to the read pulse, an image (Video) signal is read out of the photoelectric conversion elements and is A/D converted.
At this time, in the example of FIG. 11, an A/D conversion range is level shifted in accordance with a range of the image signal. In the example of FIG. 12, the pixel signal is level shifted in accordance with an A/D conversion range. In each of the above examples, the A/D conversion is performed between the maximum and minimum values of the image signal.
An in-focus state can be discriminated by executing the calculation disclosed in Japanese Laid-Open Patent Gazette Nos. 58-142306, 59-107313, 60-101513, or Japanese Patent Application No. 61-160824 on the basis of the digital pixel signal obtained as mentioned above.
However, in the above conventional photoelectric converting apparatus, the image signal and the maximum and minimum values of the image signal and of the accumulation signal of the photoelectric conversion element array are output through different read-out circuits respectively, so that there is a case where there are deviations between the actual maximum and minimum values of the pixel signal and the values of V.sub.max and V.sub.min because of causes such as difference of the read-out gain, mismatching among the amplifiers 9, 13, and 14, or the like. On the other hand, as shown in the examples of FIGS. 11 and 12, when the accumulation charges are controlled on the basis of the difference between V.sub.max and V.sub.min, there is a case where a part of the image signal exceeds the A/D conversion range.
The difference of the read-out gain occurs as follows. For instance, in FIG. 7, assuming that a capacity of the accumulation capacitor 5-1 is set to C.sub.T1 and a parasitic capacity of the read-out line 7 is set to C.sub.H, in the case where an emitter potential V.sub.E1 of the photo transistor 1--1 was read out to the read-out line 7, an output becomes ##EQU1## V.sub.E1 and the gain is not set to 1.
On the other hand, since the V.sub.min and V.sub.max outputs are read out at the gain 1, a deviation occurs.